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features ? single supply voltage range, 2.7v to 3.6v ? single supply for read and write ? fast read access time ? 90 ns ? internal program control and timer ? 8k bytes boot block with lockout ? fast erase cycle time ? 10 seconds ? byte-by-byte programming ? 30 s/byte typical ? hardware data protection ? d a t a polling for end of program detection ? low power dissipation ? 25 ma active current ? 50 a cmos standby current ? typical 10,000 write cycles ? green (pb/halide-free) packaging option 1. description the at49bv512 is a 3-volt only, 512k flash memories organized as 65,536 words of 8 bits each. manufactured with atmel?s advanced nonvolatile cmos technology, the devices offer access times to 90 ns with power dissipation of just 90 mw over the commercial temperature range. when the devices are deselected, the cmos standby current is less than 50 a. to allow for simple in-system reprogrammability, the at49bv512 does not require high input voltages for programming. three-volt only commands determine the read and programming operation of the device. reading data out of the device is similar to reading from an eprom. reprogramming the at49bv512 is performed by erasing the entire 1 megabit of memory and then programming on a byte-by-byte basis. the typical byte programming time is a fast 30 s. the end of a program cycle can be optionally detected by the data polling feature. once the end of a byte program cycle has been detected, a new access for a read or program can begin. the typical num- ber of program and erase cycles is in excess of 10,000 cycles. the optional 8k bytes boot block section includes a reprogramming write lock out fea- ture to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. 512k (64k x 8) single 2.7-volt battery-voltage flash memory at49bv512 not recommended for new design 1026g?flash?10/05
2 1026g?flash?10/05 at49bv512 2. pin configurations 18 2.1 32vsop/32tsop (type 1) top view 2.2 32plcc top view pin name function a0 - a15 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc nc a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 nc nc vcc we nc
3 1026g?flash?10/05 at49bv512 3. block diagram 4. device operation 4.1 read the at49bv512 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever c eor o e is high. this dual-line control gives designers flexibility in preventing bus contention. 4.2 erasure before a byte can be reprogrammed, the 64k bytes memory array (or 56k bytes if the boot block featured is used) must be erased. the erased state of the memory bits is a logical ?1?. the entire device can be erased at one time by using a 6-byte software code. the software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the chip erase cycle waveforms). after the software chip erase has been initiated, the device will internally time the erase opera- tion so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . if the boot block lockout feature has been enabled, the data in the boot sector will not be erased. 4.3 byte programming once the memory array is erased, the device is programmed (to a logical ?0?) on a byte-by- byte basis. please note that a data ?0? cannot be programmed back to a ?1?; only erase opera- tions can convert ?0?s to ?1?s. programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the command definitions table). the device will automatically generate the required internal program pulses. the program cycle has addresses latched on the falling edge of we or ce, whichever occurs last, and the data latched on the rising edge of w eor c e, whichever occurs first. program- ming is completed after the specified t bp cycle time. the d a t a polling feature may also be used to indicate the end of a program cycle. 4.4 boot block programming lockout the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 8k bytes. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have data inputs/outputs i/o0 - i/o7 data latch input/output buffers y-gating main memory (56k bytes) optional boot block (8k bytes) oe, ce and we logic y decoder x decoder vcc gnd oe we ce address inputs 1fffh 2000h ffffh 0000h
4 1026g?flash?10/05 at49bv512 to be activated; the boot block?s usage as a write protected region is optional to the user. the address range of the boot block is 0000h to 1fffh. once the feature is enabled, the data in the boot block can no longer be erased or pro- grammed. data in the main memory block can still be changed through the regular programming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the ?command defi- nition table? on page 5 . 4.4.1 boot block lockout detection a software method is available to determine if programming of the boot block section is locked out. when the device is in the software product identification mode (see software product identification entry/exit sections on page 12 ) a read from address location 00002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be pro- grammed; if the data on i/o0 is high, the program lockout feature has been activated and the block cannot be programmed. the software product identification code should be used to return to standard operation. 4.5 product identification the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ?operating modes? on page 6 (for hardware operation) or software product identification entry/exit sections on page 12 . the manufacturer and device code is the same for both modes. 4.6 data polling the at49bv512 features d a t a polling to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all out- puts and the next cycle may begin. d a t a polling may begin at any time during the program cycle. 4.7 toggle bit in addition to data polling the at49bv512 provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. 4.8 hardware data protection hardware features protect against inadvertent programs to the at49bv512 in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) pro- gram inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (c) noise filter: pulses of less than 15 ns (typical) on the w eor c e inputs will not initiate a program cycle. 4.9 input levels while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs ( oe, c eand w e) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v.
5 1026g?flash?10/05 at49bv512 notes: 1. the 8k byte boot sector has the address range 0000h to 1fffh. 2. either one of the product id exit commands can be used. 5. command definition table command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 byte program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (1) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 6. absolute maximum ratings* temperature under bias ............................... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
6 1026g?flash?10/05 at49bv512 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh, device code: 03h. 5. see details under software product identification entry/exit sections on page 12 . note: 1. in the erase mode, i cc is 50 ma. 7. dc and ac operating range at49bv512-90 at49bv512-12 operating temperature (case) com. 0 c-70 c ind. -40 c-85 c v cc power supply 2.7v to 3.6v 2.7v to 3.6v 8. operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a15 = v il ,a9=v h , (3) ,a0=v il manufacturer code (4) a1 - a15 = v il ,a9=v h , (3) ,a0=v ih device code (4) software (5) a0 = v il ,a1-a15=v il manufacturer code (4) a0 = v ih ,a1-a15=v il device code (4) 9. dc characteristics symbol parameter condition min max units i li input load current v in =0vtov cc 10 a i lo output leakage current v i/o =0vtov cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 50 a i sb2 v cc standby current ttl ce = 2.0v to v cc 1ma i cc (1) v cc active current f = 5 mhz; i out =0ma 25 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a; v cc = 3.0v 2.4 v
7 1026g?flash?10/05 at49bv512 11. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc -t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l - 5 pf). 4. this parameter is characterized and is not 100% tested. 10. ac read characteristics symbol parameter at49bv512-90 at49bv512-12 units min max min max t acc address to output delay 90 120 ns t ce (1) ce to output delay 90 120 ns t oe (2) oe to output delay 0 40 0 50 ns t df (3)(4) ce or oe to output float 0 25 0 30 ns t oh output hold from oe, ce or address, whichever occurred first 00ns address ce output oe output valid address valid high z
8 1026g?flash?10/05 at49bv512 12. input test waveforms and measurement level 13. output test load note: 1. this parameter is characterized and is not 100% tested. 14. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 4 6 pf v in =0v c out 812pfv out =0v ac driving levels ac measurement level 0.4v 1.5v 2.4v t r ,t f 5ns 100 pf 1.3k 1.8k 3.0v output pin
9 1026g?flash?10/05 at49bv512 16. ac byte load waveforms 16.1 we controlled 16.2 ce controlled 15. ac byte load characteristics symbol parameter min max units t as ,t oes address, oe set-up time 0 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 200 ns t ds data set-up time 100 ns t dh ,t oeh data, oe hold time 0 ns t wph write pulse width high 200 ns address ce data i n we oe address we data i n ce oe
10 1026g?flash?10/05 at49bv512 18. program cycle waveforms 19. chip erase cycle waveforms note: oe must be high only when we and ce are both low. 17. program cycle characteristics symbol parameter min typ max units t bp byte programming time 30 s t as address set-up time 0 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 0 ns t wp write pulse width 200 ns t wph write pulse width high 200 ns t ec erase cycle time 10 seconds ce we data a0-a15 oe 5555 2aaa 5555 aa 55 a0 address program cycle input data ce we data a0-a15 oe 5555 2aaa 5555 aa 55 80 5555 2aaa 5555 aa 55 10 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5
11 1026g?flash?10/05 at49bv512 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 21. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 23. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 20. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns ce oe i/o7 we an a0-a15 an an an an 22. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns ce oe i/o6 we
12 1026g?flash?10/05 at49bv512 24. software product identification entry (1) 25. software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a15 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does note remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturers code: 1fh device code: 03h. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) load data f0 to any address exit product identification mode (4) or 26. boot block lockout feature enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second (2)
13 1026g?flash?10/05 at49bv512 27. ordering information note: 1. the at49bv512 has as optional boot block feature. the part number shown in the ordering information table is for devices with the boot block in the lower address range (i.e., 0000h to 1fffh). users requiring boot block protection to be in the higher address range should contact atmel. 27.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 120 25 0.05 at49bv512-12jc 32j commercial (0 c-70 c) 27.2 green package (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 90 25 0.05 at49bv512-90ju AT49BV512-90TU at49bv512-90vu 32j 32t 32v industrial (-40 c-85 c) package type 32j 32-lead, plastic j-leaded chip carrier package (plcc) 32t 32-lead, thin small outline package (tsop) (8 x 20 mm) 32v 32-lead, thin small outline package (vsop) (8 x 14 mm)
14 1026g?flash?10/05 at49bv512 28. packaging information 28.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45 pin no. 1 identifier 1.14(0.045) x 45 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010 (0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004 (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
15 1026g?flash?10/05 at49bv512 28.2 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
16 1026g?flash?10/05 at49bv512 28.3 32v ? vsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32v , 32-lead (8 x 14 mm package) plastic thin small outline package, type i (vsop) b 32v 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation ba. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 13.80 14.00 14.20 d1 12.30 12.40 12.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
17 1026g?flash?10/05 at49bv512 29. revision history revision no. history revisio nf?a ugust 2004 ? added a 55 ns speed option and removed the 90, 120, and 150 ns speed options for the die shrink redesign. the pdip package was also eliminated. the die shrink redesign will have a marketing revision letter ?a? marked after the date code on the topside of the device. revisio n g ? oct. 2005 ? added 120 ns plcc commercial option. added 90 ns green option. removed 55 ns speed option.
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